The present invention relates to a microprocessor having a dynamic memory refresh circuit, and particularly to a microprocessor capable of accessing an external dynamic memory in which a refresh operation of stored information is required.
It is well known that information stored in a dynamic memory must be refreshed at predetermined time intervals. In general, a refresh operation is controlled by a refresh controller generating sequential refresh addresses and is performed by means of sense amplifiers coupled to bit lines in a dynamic memory. In the refresh operation, information stored in all memory cells coupled to a word line activated by one refresh address are simultaneously refreshed. Since all information stored in the dynamic memory must be refreshed, a plurality of refresh addresses for activating all word lines are to be generated by the refresh controller. A refresh cycle is predetermined in accordance with a dynamic memory to be used. In a 64K dynamic memory, for example, 128 refresh addresses are required to active all of the 128 word lines for the refresh operation within normally
There are other types of memories such as a static memory which does not require refresh operation and a pseudo-static memory which includes a refresh controller and performs a self-refresh operation. However, these memories are expensive. Therefore, dynamic memories having no refresh controller are widely used in a low-cost processing system or in a system with a large memory capacity.
As described above, refresh addresses have to be applied to these dynamic memories from external terminals at the predetermined time intervals. Further, in order to avoid an application of the refresh addresses, a dynamic memory including a counter for generating sequential refresh addresses is provided. In such dynamic memory, however, a timing signal for controlling a count operation according to a predetermined time interval must be applied to the counter from external of the memory.
For the reason described above, a data processing system employing a dynamic memory is provided with a refresh controller to generate refresh addresses and/or a refresh timing signal. The refresh controller is in general provided separately from or independently of a microprocessor having a central processing unit (CPU). However, since both the refresh controller and CPU can not simultaneously access the same memory, the refresh controller must request the CPU to allow a memory access. This request is conventionally done by means of an interrupt. In response to reception of the interruption signal from the refresh controller the CPU sends an access grant signal to the refresh controller when the CPU is not in operation. If the CPU is performing an operation, the access grant signal is not sent to the refresh controller until that operation is finished. When the access grant signal is applied to the refresh controller, the refresh controller starts the refresh operation by using a signal bus to which the dynamic memory, the refresh controller and the CPU are coupled.
It is to be noted that the CPU can not access both the dynamic memory and the bus during the refresh operation. Namely, an operation of the CPU is stopped in the period of the refresh operation. Particularly, even if the operation to be performed by the CPU does not require the dynamic memory access but requires an access to a peripheral equipment, CPU, ROM, or the like which is commonly coupled to the bus, the CPU can not access them because the bus is busy in the refresh operation. Further the CPU has to stop its operation periodically with a time interval to carry out the memory refresh operation. Thus, in the case the operating frequency of the microprocessor is, for instance, 4 MHz, the processing capability of the microprocessor which is stopped by the refresh operation will decrease by about 10% in comparison with that of the microprocessor which does not participate in the refresh operation.
On the other hand there is a microprocessor which involves a refresh control circuit sending a refresh address to a dynamic memory at the predetermined timing in the CPU execution cycle. However, the microprocessor of this type has such shortcomings that a refresh operation can not be performed when the CPU is in a wait condition because in this period the CPU execution cycle is indefinite. Furthermore, in the case a microprocessor includes an instruction prefetch circuit which reads instructions to be executed by a CPU out of an external ROM and preliminarily stores a plurality of the read-out instructions, the signal bus to which the ROM and the dynamic memory are coupled is employed not only by the CPU but also by the instruction prefetch circuit. In general, access to the ROM and the dynamic memory are independently and asynchronously performed. Therefore, the above-mentioned refresh control circuit can not be adapted to the microprocessor including the instruction prefetch circuit.